# CHECKLISTS.md

## Pre-Architecture Sanity Checklist

- [ ] All top-level requirements are quantified and traceable to a verification method
- [ ] Power budget closed for all operating modes (sleep/active/peak) with ≥ 25 % margin
- [ ] Thermal budget and derating strategy defined for worst-case ambient and load
- [ ] Mechanical envelope, connector locations, and mounting features frozen
- [ ] Regulatory/certification targets identified with rough cost and timeline
- [ ] Supply-chain risk (single-source, lead time, geopolitical) assessed at architecture level

## Schematic Review — Power Domain (Mandatory)

- [ ] Every power pin has local 100 nF (or per datasheet) + appropriate bulk; placed < 3 mm from pin
- [ ] High di/dt return currents do not travel through narrow or distant vias
- [ ] Sequencing and reset timing meet all devices under min/max voltage and load simultaneously
- [ ] Protection (reverse polarity, over-voltage, ESD, fusing) present on all external power ports
- [ ] Current limits and eFuses sized for both normal and fault conditions

## Schematic Review — Digital & Interface

- [ ] No floating digital inputs (tied or pulled to valid level per datasheet)
- [ ] I2C/SPI/UART pull-ups, terminations, and series resistors correct for speed and loading
- [ ] Test access points (JTAG/SWD, UART, key GPIOs, all power rails) present on every major device
- [ ] Level translation strategy correct and bidirectional where required

## Layout Review — Top 10 Risks

1. Return path discontinuities or slots under high-speed or high-current traces
2. Insufficient stitching via density around plane splits, board edges, or RF sections
3. Thermal reliefs or inadequate copper weight/thermal vias under power components
4. Acute angles or uncontrolled impedance on > 1 Gbps or RF traces
5. Decoupling loops larger than datasheet maximum or poor via placement
6. Antenna keep-out violated or poor reference plane under RF
7. Creepage/clearance violations (post-conformal coat)
8. Mechanical keep-ins violated by tall parts or test points
9. Copper imbalance causing warpage on large/thin boards
10. Missing or poorly placed fiducials, tooling holes, and panel features

## Bring-Up & Debug Checklist

- [ ] Visual + X-ray inspection of BGAs, QFNs, and thermal pads before first power
- [ ] First power applied with current-limited supply; all rails monitored for sequencing and inrush
- [ ] JTAG/SWD connectivity and boundary scan verified before full firmware load
- [ ] Clock presence, frequency, and jitter measured
- [ ] Power rail noise/ripple captured under realistic dynamic loads
- [ ] Thermal imaging within 5 minutes of power-on; hotspots logged
- [ ] Full functional test matrix executed and logged before environmental or stress testing

## Production Readiness Gates

- [ ] ≥ 95 % first-pass yield on pilot build with clear Pareto of remaining defects
- [ ] All high-RPN failure modes mitigated or formally accepted with data
- [ ] Test fixtures validated for coverage, repeatability, and false-fail rate
- [ ] A-item components dual-sourced or protected by buffer stock
- [ ] All required regulatory certificates in hand with demonstrated margin

*Treat these checklists as living documents. Add project-specific items and mark sign-off with engineer initials and date.*