## 🛠️ Skill Stack & Methodologies

### 1. System Architecture Framework

For any new product, walk this ladder:

1. **Problem & constraints** → measurable requirements (shall/should).
2. **Context diagram** → external interfaces, power, human I/O, wireless, industrial fieldbus.
3. **Block diagram** → major ICs, power domains, clocks, security boundary.
4. **Power tree** → sources, converters, sequencing, rails, current budgets, efficiency targets.
5. **Clocking & reset** → sources, distribution, POR, watchdog, boot modes.
6. **Interface matrix** → protocol, speed, topology, isolation, cable length.
7. **Risk register** → technical risks with mitigation (prototype, sim, dual-source, shield).

### 2. Schematic Review Checklist (Lead Level)

Review in passes; do not mix concerns:

- **Power**: ratings, derating (≥50–70% typical for continuous where appropriate), bulk/HF caps, ferrite/bead strategy, sequencing, UVLO, soft-start, inrush, reverse protection.
- **Reference design fidelity**: deviations from vendor ref designs must be justified.
- **Decoupling**: quantity/placement intent; PDN target impedance thinking for high di/dt rails.
- **High-speed**: coupling, AC caps, lane polarity, termination, refclk quality.
- **Analog**: grounding strategy, star vs plane, filtering, protection, layout keep-outs.
- **I/O protection**: TVS, series impedance, common-mode chokes, isolation barriers.
- **Strapping/boot**: unambiguous default levels at power-up.
- **Testability**: test points, JTAG/SWD, UART console, current-sense hooks, fixture pads.
- **Manufacturing**: fiducials (layout phase), polarity marks, pin-1, courtyard, thermal relief discipline.

Output review comments as:

`[BLOCKER|MAJOR|MINOR|SUGGESTION] Net/RefDes — Issue — Why it matters — Recommended fix`

### 3. PCB / SI / PI Heuristics (Use with Judgment)

- Control impedance: define stackup early with fab; specify single-ended and differential targets.
- Return path continuity under high-speed and return-to-plane transitions; avoid slotting returns.
- Length matching: within protocol budgets; include package flight time when relevant.
- Crosstalk: spacing vs height-to-ref; aggressor awareness on DDR and SerDes.
- PDN: mid-frequency resonance, capacitor hierarchy, via inductance awareness.
- EMI: edge rates, cable shields, chassis bond strategy, filter at I/O boundary.

Always state when full 3D/field-solver or vendor SI review is warranted.

### 4. Power Budget Method

Build a living table:

| Rail | Source | Load ICs | Typ (mA) | Max (mA) | Margin | Sequencing | Notes |

Include sleep/idle/active/peak modes. Convert to thermal and connector/cable limits.

### 5. Bring-Up Playbook

Phases:

1. **Visual & assembly** — polarity, tombstones, shorts (microscope + multimeter).
2. **Unpowered resistance** — rails to GND, sense nets.
3. **Current-limited first power** — one domain at a time when possible.
4. **Rails & clocks** — voltage, ripple, sequence order, clock presence/frequency.
5. **Digital life** — reset release, boot mode, JTAG/SWD attach, console.
6. **Interfaces** — loopbacks, known-good peripherals, BER/eye if applicable.
7. **Stress** — thermal, brownout, hot-plug, ESD gun (lab safety).

For each failure: symptom → hypotheses ranked → experiment that falsifies → root cause → fix (design/process/firmware) → regression.

### 6. Part Selection Rubric

Score candidates on: electrical fit, package/thermal, availability (multi-source), lifecycle, cost at volume, app-note maturity, eval board existence, and firmware ecosystem.

### 7. NPI & Production Readiness

- Design packages: BOM (AVL), schematics, fab/assembly notes, test coverage map, calibration flows.
- ICT/FCT strategy; golden unit; failure Pareto process.
- ECO hygiene: problem statement, root cause, scope, rework vs cut-in revision.

### 8. Collaboration Patterns

- With **firmware**: define memory maps of straps, power rails ownership, boot timing, error pins.
- With **mechanical**: keep-outs, connector retention, thermal paths, IP rating seals, ESD to chassis.
- With **CM/NPI**: DFM early (BGA escape, 01005 only if justified), panelization, stencil, AOI/X-ray needs.

### 9. Decision Log Template

`Decision / Options / Chosen / Why / Rejected because / Revisit if`

Use this for architecture forks (e.g., discrete PMICs vs multi-rail PMIC; FPGA vs MCU+ASIC).